1. Field of the Invention
The present invention generally relates to a method for forming DRAM cell, and more specifically, to a method for forming a DRAM cell wherein a semiconductor substrate having an n+ buried layer is etched to form a contact hole for storage electrode, and a MOS transistor of vertical structure having the n+ buried layer as an impurity region is formed therein to allow read and write operations without loss of charges due to leakage currents.
2. Description of the Prior Art
FIGS. 1a through 1e are cross-sectional diagrams illustrating a conventional method for forming a DRAM cell.
Referring to FIG. 1a, a MOS transistor 15 having a gate electrode 17 is formed on a semiconductor substrate 11 including a device isolation film 13 defining an active region. The gate electrode 17 has a hard mask layer 19 thereon and a gate oxide film (not shown) thereunder. An insulating film spacer 21 is disposed on a side wall of the gate electrode 17.
Referring to FIG. 1b, a first interlayer insulating film 23 is formed on the entire surface and then planarized.
Thereafter, the first interlayer insulating film 23, the gate oxide film and the semiconductor substrate 11 are etched via a photolithography process using a storage electrode contact mask to form a trench 25.
Referring to FIG. 1c, a polysilicon liner layer(not shown) is formed on the entire surface, and then planarized via chemical mechanical polishing process to expose the first interlayer insulating film 23, thereby forming a storage electrode 27 on the inner wall of the trench 25.
Referring to FIG. 1d, a dielectric film 29 and a polysilicon layer for plate electrode are sequentially formed on the entire surface. The polysilicon layer for plate electrode and the dielectric film 29 are etched via a photolithography process using a plate electrode mask to form a plate electrode 31.
Referring to FIG. 1e, a second interlayer insulating film 33 is formed on the entire surface and then planarized.
Thereafter, the second interlayer insulating film 33, the first interlayer insulating film 33 and the gate oxide film are etched via a photolithography process using a bit line contact mask to form a bit line contact hole. A bit line 35 is then formed by filling up the bit line contact hole.
In accordance with the above-described conventional method for forming DRAM cell, data stored in the cell is lost due to leakage currents such as a leakage current in a capacitor and a leakage current between device isolation films, resulting in degradation of refresh characteristics and requirement of capacitors having large capacitance.
It is an object of the present invention to provide a method for forming DRAM cell wherein a MOS transistor of vertical structure having an n+ buried layer on a semiconductor substrate as an impurity region is formed in a contact hole for storage electrode to allow read and write operations without loss of charges due to leakage currents.
In order to achieve the above object of the present invention, the method for forming a DRAM cell comprises the steps of: forming a buried layer by implanting a high concentration impurity into a semiconductor substrate; forming a MOS transistor having a first gate oxide film, a first gate electrode, a source and drain region; forming a planarized first interlayer insulating film on the entire surface; etching a portion of the first interlayer insulating film on the drain region, the drain region, and a portion of the semiconductor substrate below the drain region to expose the buried layer, whereby forming a contact hole for storage electrode; forming a vertical MOS transistor in the contact hole by forming a second gate oxide film pattern whose both ends are respectively overlapped on the drain regions and a second gate electrode overlapped on the second gate oxide; forming a storage electrode on the second gate electrode so that the both ends are repectively extending on the drain regions; forming a dielectric layer and a plate electrode on the storage electrode; forming a planarized second interlayer insulating film on the entire surface; sequentially etching the second interlayer insulating film and the first interlayer insulating film on the source region to expose the source region, whereby forming a bit line contact hole; and forming a bit line contacting the source region through bit line contact hole.